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TOSHIBA
TB62726AN, TB62726AF
TOSHIBA Bi-CMOS INTEGRATED CIRCUIT SILICON MONOLITHIC
T B 6 2 7 2 6 A N, T B 6 2 7 2 6 A F
16-bit constant current LED driver with operation supply of 3.3V to 5V
The TB62726A series are comprised of constant-current drivers designed for LEDs and LED displays. The output current value can be set using an external resistor. As a result, all outputs will have virtually the same current levels. This driver incorporates 16-bit constant-current outputs, a 16-bit shift register, a 16-bit latch and 16-bit AND-gate circuit. These drivers have been designed using the Bi-CMOS process.
TB62726AN
Feature
*Output current capability and the number of output: P-SDIP24-300-1.78 90 mA x 16 outputs TB62726AF *Constant current range : 2 to 90 mA *Application output voltage : 0.7V (output current 2 to 80mA) 0.4V (output current 2 to 40mA) *For anode common LED *Input signal voltage level : 3.3V-5.0V CMOS level (schmitt trigger input) P-SSOP24-300-1.00B *Power supply voltage range VDD=3.0 to 5.5V *Muximum output terminal voltage 17V *Serial and parallel data transfer rate 20 MHz (min., Cascade Connection) *Operation temperature range topr = -40 to 85 degrees *Package : AN type - - - P-SDIP-300-1.78 AF type - - - P-SSOP24-300-1.00B *Current accuracy (not used dot-current correction.)
Output voltage >= 0.4V >= 0.7V Current accuracy between bits +/- 4 % between ICs +/- 12 % Output current 2 to 40 mA 2 to 90 mA
TB62726AN, TB62726AF (Ver.5) 2002, Nov. 20th page 1/16
TOSHIBA
Package and pin layout ( Top view )
GND SERIAL-IN CLOCK LATCH OUT 0 OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7
TB62726AN, TB62726AF
VDD R-EXT SERIAL-OUT ENABLE OUT 15 OUT 14 OUT 13 OUT 12 OUT 11 OUT 10 OUT 9 OUT 8
Warnings : Short-circuiting an output terminal to GND or to the power supply terminal may broken the device. Please take care when wiring the output terminals, the power supply terminal and the GND terminals.
Block Diagram
OUT0 R-EXT I-REG OUT1 OUT15
ENABLE Q ST D LATCH Q ST D Q ST D
SERIAL-IN
DQ CK
DQ CK
DQ CK
SERIAL-OUT
CLOCK
Truth Table
CLOCK Positive edge Positive edge Positive edge Negative edge Negative edge LATCH H L H X X ENABLE L L L L H SERIAL-IN Dn Dn+1 Dn+2 Dn+3 Dn+3 OUT0 --- OUT7 --- OUT15 Dn --- Dn-7 --- Dn-15 No Change Dn+2 --- Dn-5 --- Dn-13 Dn+2 --- Dn-5 --- Dn-13 Off SERIAL-OUT Dn-15 Dn-14 Dn-13 Dn-13 Dn-13
Note 1: OUT0~OUT15=ON when Dn=H ; OUT0~OUT15=OFF when Dn=L In order to ensure that the level of the power supply voltage is correct, an external resistor have to connected between R-EXT and GND.
TB62726AN, TB62726AF (Ver.5) 2002, Nov. 20th page 2/16
TOSHIBA
Timing diagram
n=0 1 2 3 4 5 6 7 8 9 101112131415 CLOCK
TB62726AN, TB62726AF
3.3v/5v 0V 3.3v/5v 0V 3.3v/5v 0V 3.3v/5v 0V On Off On Off On Off
SERIAL-IN
LATCH
ENABLE
OUT0
OUT1
OUT3
OUT15
On Off 3.3v/5v 0V
SERIAL-OUT
Warning : Latch circuit is leveled-latch circuit. Be careful because it is not triggered-latch circuit. Note 2 : The latches circuit holds data by pulling the LATCH terminal Low. And, when LATCH terminal is a High-level, latch circuit doesn't hold data, and it passes from theInput to the output. When ENABLE terminal is Low-level, output terminal OUT0~OUT15 respond to the data, and on & off does. And, when ENABLE terminal is a High-level, it offs with the output terminal regardless of the data.
TB62726AN, TB62726AF (Ver.5) 2002, Nov. 20th page 3/16
TOSHIBA
Terminal description
Pin No. 1 2 3 4 5 ~ 20 OUT 0 ~ 15 21 22 23 24 Pin Name GND SERIAL-IN CLOCK LATCH
TB62726AN, TB62726AF
Function GND terminal for control logic Input terminal for serial data for data shift register Input terminal for clock for data shift on rising edge Input terminal for data strobe When the LATCH=High-level, data is no latched. When ithe LATCH=Low-level, data is latched. Constant-current output terminals
Input terminal for output enable. All outputs (OUT0 ~ OUT15 ) are turned off, when the ENABLE=High-level. And are turned on, when the ENABLE=Low-level. SERIAL-OUT Output terminal for serial data input on SERIAL-IN terminal R-EXT Input terminal used to connect an external resistor. This regulated the output current. VDD 3.3V - 5V supply voltage terminal. ENABLE
Equivalent circuit of inputs and output
1. ENABLE Terminal VDD ENABLE GND 3. CLOCK,SERIAL-IN Terminal VDD CLOCK, SERIAL - IN GND 5. OUT0 ~ 15 Terminal OUT 0 ~ 15
Parasitic Diode
2. LATCH Terminal
R(UP) 200k
VDD LATCH GND
250k R(DOWN)
4. SERIAL-OUT Terminal VDD Internal data GND SERIAL - OUT
GND
TB62726AN, TB62726AF (Ver.5) 2002, Nov. 20th page 4/16
TOSHIBA
Absolute maximum ratings
Characteristics Supply Voltage Input Voltage Output Current Output Voltage Power Dissipation Thermal Resistance Operating Temperature Storage Temperature Symbol VDD VIN IOUT VOUT Pd1 Pd2 Rth(j-a)1 Rth(j-a)2 Topr Tstg Rating +6
TB62726AN, TB62726AF
Unit V mA/ch V W degree/W degree
-0.2 to VDD+0.2 +90 -0.2 to 17 AN type : 1.25(Free air), 1.78(On PCB) AF type : 0.83(Free air), 1.00(On PCB) AN type : 104(Free air), 70(On PCB) AF type : 140(Free air), 120(On PCB) -40 to 85 -55 to 150
Note 3: AN-type: Powers dissipation is derated by 14.28 mW/degree if device is mounted on PCB and ambient temperature is above 25 degree. FN-type: Powers dissipation is derated by 6.67 mW/degree if device is mounted on PCB and ambient temperature is above 25 degrees. With devide monuted on glass-epoxy PCB of less than 40% Cu and of dimensions 50mm x 50 mm x 1.6mm.
Recommended operating condition ( Topr = -40~85 degree, unless otherwise noted. )
Characteristics Supply Voltage Output Voltage Output Current Symbol VDD VOUT(On) IOUT IOH IOL Input Voltage Clock Frequency LATCH Pulse Width CLOCK Pulse Width ENABLE Pulse Width When the pulse of the Low level is inputted to the ENABLE terminal held in the H level. Setup Time for CLOCK Terminal Hold Time for CLOCK Terminal Setup Time for /LATCH Terminal VIH VIL fCLK tw LATCH tw CLOCK Upper IOUT=20mA tw ENABLE Lower IOUT=20 mA t SETUP1 t HOLD t SETUP2 50 3000 10 10 ns Cascade Connected Condition Each DC 1 Circuit SERIAL-OUT Min 3 2 0.7VDD -0.15 50 25 2000 Typ 0.7 Max 5.5 4 80 -1 1 VDD+0.15 0.3xVDD 20 Unit V V mA/ch mA V MHz
Note 4: When the pulse of the "L" level is inputted to the ENABLE terminal held in the "H" level.
TB62726AN, TB62726AF (Ver.5) 2002, Nov. 20th page 5/16
TOSHIBA
Characteristics Supply voltage Symbol VDD IOUT1 IOUT2 IOUT3 IOUT4 dIOUT1 dIOUT2 IOZ VIN VOL VOH %/VDD R(UP) R(DOWN) IDD(OFF)1 IDD(OFF)2 IDD(OFF)3 Condition Normal operation VOUT=0.4V,VDD=3.3V REXT= VOUT=0.4V,VDD=5V 490 ohm VOUT=0.7V,VDD=3.3V REXT= VOUT=0.7V,VDD=5V 250 ohm VOUT=0.4V, REXT=490 ohm All output ON VOUT=0.4V, REXT=250 ohm VOUT=15V IOL=+1 mA, Vdd=3.3V IOL=+1 mA, Vdd=5V IOH=-1 mA, Vdd=3.3V IOH=+1 mA,Vdd=5V When VDD is changed 3V to 5.5V ENABLE terminal LATCH terminal REXT=Open, VOUT=15V REXT=490ohm All output OFF, VOUT=15V REXT=250ohm All output ON, REXT=490ohm VOUT=0.7V Ta= -40degree, Same as the avobe. All output ON, REXT=250ohm VOUT=0.7V Ta= -40 degree, Same as the avobe.
TB62726AN, TB62726AF
Electrical characteristics ( VDD=3V to 5.5V, Topr=25degree unless otherwise noted.)
Min 3.0 31.96 31.59 63.63 62.75 Typ 36.20 35.90 72.30 71.30 Max 5.5 40.54 40.20 80.97 79.95 Unit V
Output current
mA
Output current error between bits Output leakage Current Input voltage Input voltage
-
+/-1
+/-4
%
0.7VDD GND .3 4.7 . 115 .1 .4 -
-1 230 0.1 3.5 6 9 18 -
1 VDD 0.3VDD 0.3 0.3 -5 460 0.5 5 9 15 20 25 40
A V
SOUT terminal Voltage Output current supply voltage regulation Pull up resistor Pull down resistor
V
%/V
Supply current
IDD(ON)1
Ohm
IDD(ON)2
TB62726AN, TB62726AF (Ver.5) 2002, Nov. 20th page 6/16
TOSHIBA
Switching characterictics (Topr=25degree, unless otherwise noted )
Characteristics Symbol tpLH1 tpLH2 tpLH3 Propagation delay tpLH tpHL1 tpHL2 tpHL3 tpLH Output rise time tor Condition CLK-OUTn, LATCH="H", ENABLE="L" LATCH-OUTn, ENABLE="L" ENABLE-OUTn, LATCH="H" CLK-SERIALOUT CLK-OUTn, LATCH="H", ENABLE="L" LATCH-OUTn, ENABLE="L" ENABLE-OUTn, LATCH="H" CLK-SERIAL-OUT Voltage waveform 10%~90%
TB62726AN, TB62726AF
Min 3 4 40
Typ 150 140 140 6 170 170 170 7 85
Max 300 300 300 340 340 340 150
Unit
ns
tof Output fall time Voltage waveform 90%~10% 40 70 150 Maximum CLK 5 tr rise time us When not on PCB Maximum CLK 5 tf fall time Condition : (Refer to test circuit) Topr=25 degree, VDD=VIH=3.3V and 5V, VOUT=0.7V, VIL=0V,REXT=490ohms, VL=3.0V, RL=60ohms,CL=10.5pF Note 5 : If the device is connected in a cascade and tr/tf for the waveform is large, it may not be possible to achieve the timing required for data transfer. Please consider the timings carefully.
Test circuit
IDD V ,V
IH
IL
VDD ENABLE CLOCK
OUT0 C
RL
Function Generator
LATCH SERIAL-IN OUT15 SERIAL-OUT GND
L
IOL
Logic input waveform Iref VDD=VIH=3.3V VIL=0V t = t = 10ns
r f
R-EXT
CL
VL
(10% to 90%)
TB62726AN, TB62726AF (Ver.5) 2002, Nov. 20th page 7/16
TOSHIBA
Timing Waveform
1. CLOCK ,SERIAL-IN, SERIAL-OUT twCLK
TB62726AN, TB62726AF
CLOCK
50%
50%
SERIAL-IN
50%
t SETUP1 t HOLD
50%
SERIAL-OUT
50%
tpLH / tpHL 2. CLOCK, SERIAL-IN , LATCH, ENABLE, OUTn CLOCK 50%
SERIAL-IN
LATCH
t SETUP2 50% tw LAT
50%
ENABLE
tSETUP3
50%
tw ENA
50%
OUTn tpLH1 / tpHL1 3. OUTn 90% OUTn 10% tOf 10% tOr
50%
tpLH2 / tpHL2
tpLH3 / tpHL3 90%
TB62726AN, TB62726AF (Ver.5) 2002, Nov. 20th page 8/16
TOSHIBA
Output current vs duty (LEDs turn on rate)
IOUT - Duty On PCB Topr=25 degree VDD=3.3~5.0 V, Vce=1 V, Tj=120 degree max 100 90 80 70 IOUT(mA) IOUT(mA) 60 50 40 30 20 10 0 0 TB62726AF TB62726AN 100
TB62726AN, TB62726AF
IOUT - Duty On PCB Topr=55 degree VDD=3.3~5.0 V, Vce=1 V, Tj=120 degree max 100 90 80 70 60 50 40 30 20 10 0 0 TB62726AF TB62726AN 100
20 40 60 80 DUTY - Turn On Rate (%)
20 40 60 80 DUTY - Turn On Rate (%)
REXT - IOUT (Topr) Vce=0.7 V 90 80 70 60 IOUT (mA)
Topr=+25(degree)
IOUT - Duty On PCB Topr=85 degree VDD=3.3~5.0 V, Vce=1 V, Tj=120 degree max 100 90 80 70 IOUT(mA) 60 50 40 30 20 10 TB62726AF 0 TB62726AN 100
50 40 30 20 10 0 100
1000 REXT(ohm)
10000
0 20 40 60 80 DUTY - Turn On Rate (%)
Pd - Ta 2 1.8 1.6 Power dissipation P D (W/IC) 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 10 20 30 40 50 60 70 80 Ambient Temperature Ta (degree) 90 1: AF(OnPCB) 2: AN(On PCB)
TB62726AN, TB62726AF (Ver.5) 2002, Nov. 20th page 9/16
TOSHIBA
Application circuit (example 1) : The general composition in static lighting of LED.
More than VLED(V) >= Vf(total max.) +0.7 is recommended with the following application circuit with the LED power supply VLED. r1:The setup resistance for the setup of output current of every IC. r2:The variable resistance for the brightness control of every LED module. Example ) TD62M8600F : 8bit Multi-Chip PNP Tr-Array. It is unnecessary at the time of static lighting.
SCAN
VLED
Out 15 Out 0 S-IN S-OUT ENA LAT CLK 16-BIT SIPO,Latches & Constant Sink Current Drivers S-OUT 16-BIT SIPO,Latches & Constant Sink Current Drivers Out 15
Out 0 S-IN ENA LAT
C.U.
TB62726A N/F
CLK
TB62726A N/F
r1=100 ohm(min)
r1=100 ohm(min)
TB62726AN, TB62726AF
TB62726AN, TB62726AF (Ver.5) 2002, Nov. 20th page 10/16
r2
Application circuit (example 2) : When the condition of VLED is VLED > 17V.
TOSHIBA
The unnecessary voltage is one effective technique as to making the voltage descend with the zenor diode.
Example ) TD62M8600F : 8bit Multi-Chip PNP Tr-Array. It is unnecessary at the time of static lighting.
SCAN
VLED
Out 0 S-IN 16-BIT SIPO,Latches & Constant Sink Current Drivers S-OUT ENA LAT CLK S-IN ENA LAT Out 15 Out 0 16-BIT SIPO,Latches & Constant Sink Current Drivers S-OUT Out 15
C.U.
TB62726A N/F
CLK
TB62726A N/F
r1=100 ohm(min)
r1=100 ohm(min)
TB62726AN, TB62726AF
TB62726AN, TB62726AF (Ver.5) 2002, Nov. 20th page 11/16 r2
Application circuit (example 3) : When the condition of VLED is Vf+0.7VOUT=VLED-Vf=0.7~1.0V is the most suitable for VOUT.
Surplus VOUT causes an IC fever and the useless consumption electric power.
TOSHIBA
It is the one way of being effective to build in the r3 in this problem.
r3 can make a calculation to the formula r3 (ohms) = surplus VOUT / IOUT.
Though the resistance parts increase, the fixed constant current performance is kept.
Example ) TD62M8600F : 8bit Multi-Chip PNP Tr-Array. It is unnecessary at the time of static lighting.
SCAN Out 0 S-IN 16-BIT SIPO,Latches & Constant Sink Current Drivers S-OUT ENA LAT CLK ENA LAT Out 15 S-IN 16-BIT SIPO,Latches & Constant Sink Current Drivers
VLED=15V
S-OUT
C.U.
TB62726A N/F
CLK
TB62726A N/F
r1=100 ohm(min)
r1=100 ohm(min)
TB62726AN, TB62726AF
TB62726AN, TB62726AF (Ver.5) 2002, Nov. 20th page 12/16 r2
TOSHIBA
TB62726AN, TB62726AF
Note: Operating is likely to become unstable due to the electromagnetic guidance of wiring and so on. Recommend that it adjoins it and it is arranged so far as device and LED are possible. Damage by the over-voltage is likely to be suffered in LED and the output by over-voltage's occurring due to the inductance between LEDs from the output terminal. There is only one GND terminal in this device. When the inductance of the GND line, resistance element, and so on are big, it is likely to operate faultily by the GND noise when output switchings by the circuit board pattern and wiring. And, it is necessary for the REXT terminal to connect it in the GND line which became stable through the resistor. Vibration is likely to occur for the output wave form when GND was unstable and capacity (beyond 50pF) was added. Therefore, be fully careful of the circuit board pattern layout and wiring from the controller. This application circuit is a reference example, and it doesn't assure operating in all the conditions. Be sure to carry out operating confirmation. Thisdevice doesn't build in the protection circuit of over-voltage, over-current and over-temperature. Carry it out on the control side when protection is necessary. Device is likely to destroy it when it short-circuits between the output terminals to each power supply. Be fully careful of output terminal, each power supply (VDD, VLED) and the design of the GND line.
TB62726AN, TB62726AF (Ver.5) 2002, Nov. 20th page 13/16
TOSHIBA
TB62726AN, TB62726AF
Package dimmension P-SSOP24-150-0.635
TB62726AN, TB62726AF (Ver.5) 2002, Nov. 20th page 14/16
TOSHIBA
TB62726AN, TB62726AF
TB62726AN, TB62726AF (Ver.5) 2002, Nov. 20th page 15/16
TOSHIBA
TB62726AN, TB62726AF
The information contained herein is subject to change without notice. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patens or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within spacified operating ranges as set forth in the most recent products spacifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. The products described in the document may include products subject to foreign exchange and foreign trade control laws.
(C) 2000-2002 TOSHIBA CORPORATION ALL RIGHT Reserved
TB62726AN, TB62726AF (Ver.5) 2002, Nov. 20th page 16/16

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